The present disclosure relates to a programmable divider used in a phase lock loop (PLL) circuit, and more specifically, to a divider that has selectable latches having a dynamic mode and a static mode, each of which has two inputs (into a pair of parallel pass gates) and performs one of four logical operations on a received data signal. The latch in dynamic mode is suitable for high-speed applications while the latch in static mode is suitable for low speed applications. The latch in static mode also has better soft error rate (SER) tolerance. A unified latch with selectable modes in the disclosure can take advantage of both dynamic and static latches, and hence allows a circuit to operate across wide range of frequencies.
A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle.
Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs are common. One example of such use is in a divider of a phase lock loop (PLL). A PLL is a device that generates an output signal whose phase is related to the phase of the input “reference” signal. The PLL compares the phase of the input signal with the phase of the signal derived from its output oscillator using a feedback loop and adjusts the frequency of its oscillator to keep the phases matched. The feedback loop usually includes a divider, which is referred to herein as a feedback divider to distinguish it from other dividers. Such a feedback divider can effectively use LFSRs.